Eric Clever - a Life in Logic, Logic Design, Digital Design, Computer Architecture and Logic Architecture

SUMMARY OF QUALIFICATIONS

FPGA-based, real-time image processing.
Algorithm discovery, development, design and implementation in [real-time] hardware.
Video and audio compression.
Hardware and software design for embedded systems.

Embedded programming – machine code, assembly language, C, C++
Other programming languages: Pascal-Delphi, Java.
Hardware development languages: Verilog, VHDL.
Schematic capture and PCB layout: Protel (Altium), Orcad (Cadence).
FPGA toolsets: Viewlogic/Mentor, Synario (Quicklogic), plus vendor specific tooling (e.g., Xilinx ISE)
FPGA product lines: Atmel (6K, 40K), Xilinx (many), Actel (ProASIC)
Solid Modeling: AutoCad, SolidWorks

TECHNICAL ACHIEVEMENTS

Developed/invented first intelligent CCTV security system (it was designed for retail frontend loss prevention). Patents 4,145,715 and 4,237,483.
Developed/invented a real-time texture mapping system.
Developed/invented a genderless coaxial connector. Patent 5,183,409.
Developed/invented a genderless construction system. Patents 6,899,588, 6,592,421, 6,422,909, 6,325,694 and 6,231,416 (samples available on request).
Developed, for Intel, an FPGA based real-time cellular automaton, which allows for analysis of various neighborhood operations.
Developed a systolic image processing laboratory and used same to develop a 2D-barcode reader that uses a video camera and FPGA-based image processing.
Helped develop a wavelet-based, high-compression, Ethernet video camera.
Currently developing a multiple-point-of-view (MPOV) ultra high compression video camera system with one patent filed and several more in the works.

25+ years of experience in designing and building video, image processing, and camera data acquisition systems
Holds basic patents in video security system design and co-axial connectors.
Developed an intelligent video security systems and obtained patents 5,183,409 and 4,237,483. Designed and programmed embedded µPs.
Other embedded work included the design and programming of an IBM channel interface – first IBM channel I/F done with an embedded µP.
Developed internal technology that performed real-time texture mapping of live video.
Wrote a 100,000+ line (Pascal) bi-cubic rational surface modeler in support of the texture mapping project.
Consulted with Signetics on their HDL (Snap). Redesigned their FSM compiler to use Dflops.
Developed a systolic image processing laboratory (Digital Video Lab) and used same to develop a 2D-barcode reader that uses a video camera and FPGA-based image processing. DVL capabilities included real time color space conversion, YUV to HSI, HSI to RGB, RGB to HSI, real time color space manipulation, hue substitution, chroma keying and temporal differencing. Used both Atmel and Xilinix FPGAs. Used mixed methods: schematic, Verilog, VHDL and (whenever feasible) hand placed and routed. PCB designs were done with Protel and Orcad. Most of the FPGA designs were done with Viewlogic and Synario (Synario lives on in the QuickLogic tool set). This system was also used for real-time video contouring.
Developed 3D barcodes and barcode readers.
Developed IP for Atmel including a high-speed parallel arithmetic divider for their AT6000 series FPGAs.
Developed a genderless, monolithic (and multiple-contact) coaxial connector. All mechanical design work done using 3D solid modelers.
Developed (for Intel) a Real Time Cellular Automaton that allows for analysis of various neighborhood operations.
Evaluated (under contract for Xilinix) the Giga-Ops custom-computing platform for image processing tasks.
Helped develop Ethernet-connected wavelet compression cameras.
Developed a digital to tone messaging system that used the QL5232 for PCI I/F, a QL4090 as a Direct Digital Synthesizer, LVDS to communicate between the two, and a ProASIC A500K050 to drive the decoding at the other end.
Consulted on a laser-video, body-measurement system that uses Xilinx Spartan 3 FPGAs and Analog Devices TigerSHARC DSPs.
Consulted on a video-only, body-measurement system.
Designed a multi-headed metal-halide power supply (used a 400-VDC, power-factor-correction bus).
Designed various dsPIC-based systems for consumer projects.
Designed a ZigBee system for use in big-box stores.

Other
Solid modeling and mechanical design for new construction toy. Performed all of the part design work for a construction toy system. Outsourced tool design and guided the injection molding work needed to bring the toy to market.

Employment History
2001 – Present • Senior Logic Architect / Senior System Architect • HoloCam, Inc. • 3D camera systems. FPGA-based design consulting.

1998 – 2001 • System / Logic Architect • HoloCam, Inc. • 3D camera systems. FPGA-based design consulting.

1991 – 1998 • Senior Hardware and Firmware Development Engineer • Synglyphica, Inc. • Image processing product development and consulting. FPGA-based image processing and custom computing.

1983 – 1991 • Hardware and Firmware Development Engineer • Syngraphica, Inc. • Real-time virtual-reality rendering hardware and software. Real-time 3D surface morphing for texture mapping.

1980 – 1983 • Hardware and Firmware Development Engineer • Electronic Management Support, Inc. • Intelligent CCTV security systems. Digital electronic design consulting.

1978 – 1980 • Embedded Developer Programmer • Electronic Management Support, Inc. • Intelligent CCTV security systems.

1976 – 1978 • Application Programmer • AW consultants. • Real-time sales systems.

1973 – 1976 • System Programmer • Leeds & Northrup. • Real-time process control systems.

Long-Time Consulting Contracts
1978-1982 • Aydin Controls. Various embedded control systems including an IBM channel I/F.
1992-1996 • Harbor Technology / Auto Image ID. Designed, built and debugged a general purpose systolic image processing system. And used same for the initial design of their (award winning) 2D barcode reader. Then did the hardware architecture and most of the actual hardware design for their second and third generation devices.
1997-2000 • Controlled Access. Designed built and debugged various CCTV devices including digital video muxes and ethernet cameras.

Education
1973 – 1977
Temple University, Philadelphia, PA: MA Computer Science, course work for MAs in Anthropology and Philosophy (Logic).
1973
Temple University, Philadelphia, PA: BA Mathematics and Anthropology

Eric Clever
900 Briggs Road, Suite 203
Mount Laurel, NJ 08054

The following links are for two papers that we delivered at various annual PLDCons:
Real-Time Cellular Automaton
Contouring Real-Time Video

Create a Statement-of-Work (SOW) that outlines in some detail the exact task to be performed, including: functionality, schedule, deliverables (including documentation), etc.
FPGA selection.
Support-IC selection.
Begin part acquisition or arrange for an assembly house to do same.
Schematic capture – design the PCB.
Layout the PCB.
Finish part acquisition from finalized BOM.
Generate and send out the Gerber files as required by the PCB house.
When the PCBs come back send out to an assembly house for IC attach.
Meanwhile (in parallel), generate the FPGA logic design using either schematic capture tools or hardware development languages (HDLs) or both. Employ either of the standard HDLs: Verilog or VHDL. Use schematic capture and floor planners where applicable.
Write a test bench and simulate the design.
Debug the resulting design until a fully functioning prototype is achieved.
SOW check-off.
Deliver the working prototype along with all CAD files and supporting documentation.