Adder Topology Considerations
Constraints on the FPGA to MPGA Migration Path
Constraints on the FPGA to MPGA Migration Path
Brent and Kung in their widely referenced paper - A Regular Layout for Parallel Adders - ("For VLSI, regularity is one of the most important design criteria...") describe an adder topology suitable for 'regular' VLSI layout. There have been a great many adder topologies derived from the Brent and Kung [Brung] adder but any Brung derivitives that are faster use more silicon and any that use less silicon are slower. Further, most of these Brung deritives are less regular.